The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Sep. 29, 2009
Michael C. Shebanow, Saratoga, CA (US);
Jack Choquette, Palo Alto, CA (US);
Brett W. Coon, San Jose, CA (US);
Steven J. Heinrich, Madison, AL (US);
Aravind Kalaiah, Los Gatos, CA (US);
John R. Nickolls, Los Altos, CA (US);
Daniel Salinas, San Francisco, CA (US);
Ming Y. Siu, Santa Clara, CA (US);
Tommy Thorn, Milpitas, CA (US);
Nicholas Wang, Saratoga, CA (US);
Michael C. Shebanow, Saratoga, CA (US);
Jack Choquette, Palo Alto, CA (US);
Brett W. Coon, San Jose, CA (US);
Steven J. Heinrich, Madison, AL (US);
Aravind Kalaiah, Los Gatos, CA (US);
John R. Nickolls, Los Altos, CA (US);
Daniel Salinas, San Francisco, CA (US);
Ming Y. Siu, Santa Clara, CA (US);
Tommy Thorn, Milpitas, CA (US);
Nicholas Wang, Saratoga, CA (US);
Nvidia Corporation, Santa Clara, CA (US);
Abstract
A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.