The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 27, 2013

Filed:

Dec. 22, 2010
Applicants:

Ionut Cical, Dublin, IE;

Edward Cullen, Clane, IE;

Chandrika Durbha, Dublin, IE;

Inventors:

Ionut Cical, Dublin, IE;

Edward Cullen, Clane, IE;

Chandrika Durbha, Dublin, IE;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods and apparatus for receiving high voltage signals using a receiver designed in a low supply voltage technology are disclosed. One embodiment of an integrated circuit includes a single ended driver including an n-type metal-oxide-semiconductor (NMOS) transistor and a p-type metal-oxide-semiconductor (PMOS) transistor. An input pass gate is coupled to the single ended driver, and is configured as a PMOS pass gate coupled in parallel with the NMOS transistor in the single ended driver. In a low voltage mode, the NMOS transistor and the PMOS pass gate form a first pass gate for transmitting the input signal to the receiver. In a high voltage mode, the PMOS pass gate is disabled, and the NMOS transistor and PMOS transistor form a second pass gate for transmitting the input signal to the receiver.


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