The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Dec. 13, 2011
Bruce Odekirk, Bend, OR (US);
Francis K. Chai, Bend, OR (US);
Edward William Maxwell, Redmond, OR (US);
Douglas C. Thompson, Jr., Bend, OR (US);
Bruce Odekirk, Bend, OR (US);
Francis K. Chai, Bend, OR (US);
Edward William Maxwell, Redmond, OR (US);
Douglas C. Thompson, Jr., Bend, OR (US);
Microsemi Corporation, Bend, OR (US);
Abstract
A vertical-sidewall dual-mesa static induction transistor (SIT) structure includes a silicon carbide substrate having a layer arrangement formed thereon. Laterally spaced ion implanted gate regions are defined in the layer arrangement. Source regions are defined in the layer arrangement. Each of the source regions can include a channel mesa having a source mesa disposed thereon. The source mesa includes upright sidewalls relative to a principal plane of the substrate defining a horizontal dimension thereof. The channel mesa includes upright sidewalls relative to the source mesa and the principal plane of the substrate. Also disclosed is a method of fabricating a vertical-sidewall dual-mesa SiC transistor device. The method includes implanting ions at an angle relative to a principal plane of the substrate to form gate junctions in upper portions of the substrate and lateral portions of the upright channel mesas.