The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 27, 2013
Filed:
Jun. 24, 2010
Tae-young Choi, Seoul, KR;
Hi-kuk Lee, Yongin-si, KR;
Bo-sung Kim, Seoul, KR;
Young-min Kim, Yongin-si, KR;
Seung-hwan Cho, Suwon-si, KR;
Young-soo Yoon, Anyang-si, KR;
Yeon-taek Jeong, Suwon-si, KR;
Seon-pil Jang, Seoul, KR;
Tae-Young Choi, Seoul, KR;
Hi-Kuk Lee, Yongin-si, KR;
Bo-Sung Kim, Seoul, KR;
Young-Min Kim, Yongin-si, KR;
Seung-Hwan Cho, Suwon-si, KR;
Young-Soo Yoon, Anyang-si, KR;
Yeon-Taek Jeong, Suwon-si, KR;
Seon-Pil Jang, Seoul, KR;
Samsung Display Co., Ltd., , KR;
Abstract
A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate electrode disposed on an insulation substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; an etching stop layer disposed on the semiconductor; an insulating layer disposed on the gate insulating layer; and a source electrode and a drain electrode overlapping the semiconductor. The semiconductor and the gate insulating layer have a first portion on which the etching stop layer and the insulating layer are disposed, and a second portion on which etching stop layer and the insulating layer are not disposed. The source electrode and the drain electrode are disposed on the second portion of the semiconductor and the gate insulating layer.