Gate structure for field effect transistor

Abstract

A field effect transistor having a gate structure that comprises an interfacial layer positioned in between the transistor channel region and a high-K dielectric layer of the gate stack. The interfacial layer comprises AlSiO, which has a higher relative dielectric constant value than SiO. A method of forming the gate structure of a field effect transistor. The method includes forming a gate stack comprising, in order: a SiO-based layer adjacent a channel region of the field effect transistor; a high-K dielectric layer on the SiO-based layer; and a gate electrode on the high-K dielectric layer. The method also includes introducing Al into the SiO-based layer to form an AlSiOinterfacial layer in between the high-K dielectric layer and the channel region. A heating step to allows Al introduced into channel region to diffuse out of the channel region into the interfacial layer.