The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Aug. 25, 2011
Pradip Bose, Yorktown Heights, NY (US);
Gary D. Carpenter, Austin, TX (US);
Michael S. Floyd, Cedar Park, TX (US);
Eren Kursun, Yorktown Heights, NY (US);
Phillip J. Restle, Katonah, NY (US);
Michael R. Scheuermann, Yorktown Heights, NY (US);
Pradip Bose, Yorktown Heights, NY (US);
Gary D. Carpenter, Austin, TX (US);
Michael S. Floyd, Cedar Park, TX (US);
Eren Kursun, Yorktown Heights, NY (US);
Phillip J. Restle, Katonah, NY (US);
Michael R. Scheuermann, Yorktown Heights, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.