The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
May. 24, 2011
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, Ii, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, II, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and controller for implementing storage adapter performance optimization with chained hardware operations and an enhanced hardware (HW) and firmware (FW) interface minimizing hardware and firmware interactions, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; and a processor. A data store is configured to store a plurality of control blocks. A global work queue includes a plurality of the control blocks selectively arranged in a predefined chain to define sequences of hardware operations. The global work queue includes a queue input coupled to the processor and the hardware engines and an output coupled to the hardware engines. The control blocks are arranged in respective engine work queues designed to control hardware operations of the respective hardware engines and respective control blocks are arranged in an event queue to provide completion results to the processor.