The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2013

Filed:

Nov. 09, 2006
Applicants:

Chien-hsien Wu, Cupertino, CA (US);

Yook-khai Cheok, Palo Alto, CA (US);

Eugene Opsasnick, Cupertino, CA (US);

Inventors:

Chien-Hsien Wu, Cupertino, CA (US);

Yook-Khai Cheok, Palo Alto, CA (US);

Eugene Opsasnick, Cupertino, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01); G06F 13/16 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1039 (2013.01); G11C 7/1072 (2013.01); G06F 13/1668 (2013.01); G06F 13/1689 (2013.01); G06F 12/0855 (2013.01); G06F 12/0853 (2013.01);
Abstract

A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.


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