The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
May. 25, 2011
Christian Bergeron, Granby, CA;
Pascal Blais, Shefford, CA;
Clement Fortin, Granby, CA;
Luc Guerin, Granby, CA;
Christian Bergeron, Granby, CA;
Pascal Blais, Shefford, CA;
Clement Fortin, Granby, CA;
Luc Guerin, Granby, CA;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for verifying the internal microstructure of interconnects in flip-chip applications includes providing a microelectronic assembly comprising the following: a substrate hosting an array of flip-chip attach pads and one or more process control pads; a flip chip having an array of solder bumps in contact with the array of flip-chip attach pads; and one or more representative solder bumps contacting the one or more process control pads. The representative solder bumps have a substantially similar or identical chemical composition as the array of solder bumps. A reflow cycle is then applied to the microelectronic assembly to melt and solidify the array of solder bumps on the flip-chip attach pads and melt and solidify the representative solder bumps on the process control pads. The surface texture of the representative solder bumps is then optically inspected to determine an internal microstructure of the array of solder bumps.