The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2013

Filed:

Jan. 16, 2009
Applicants:

Oh-nam Kwon, Cheonan-si, KR;

Kyoung-mook Lee, Seoul, KR;

Nack-bong Choi, Suwon-si, KR;

Inventors:

Oh-Nam Kwon, Cheonan-si, KR;

Kyoung-Mook Lee, Seoul, KR;

Nack-Bong Choi, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/136 (2006.01); G02F 1/1343 (2006.01); G09G 3/36 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

An array substrate having double-layered metal patterns for use in a liquid crystal display device and a manufacturing method thereof are disclosed in the present invention. The array substrate includes a gate electrode and a gate line each having a molybdenum alloy (Mo-alloy) layer and a copper (Cu) layer configured sequentially on a substrate; a gate insulation layer on the substrate to cover the gate electrode and the gate line; an active layer arranged on the gate insulation layer in a portion over the gate electrode; an ohmic contact layer on the active layer; a data line on the gate insulation layer, the data line crossing the gate line and defining a pixel region; source and drain electrodes on the ohmic contact layer, the source electrode extending from the data line, and the drain electrode spaced apart from the source electrode; a passivation layer on the gate insulation layer covering the data line and the source and drain electrode, the passivation layer having a drain contact hole exposing a portion of the drain electrode; and a pixel electrode configured on the passivation layer in the pixel region, the pixel electrode electrically contacting the drain electrode through the drain contact hole.


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