Implementing integral dynamic voltage sensing and trigger

Abstract

A method and circuit for implementing dynamic voltage sensing and a trigger circuit, and a design structure on which the subject circuits resides are provided. The voltage sensing circuit includes a first quiet oscillator generating a reference clock, and a second noisy oscillator generating a noisy clock. A digital control loop coupled to the first quiet oscillator and the second noisy oscillator matches frequency of the first quiet oscillator and the second noisy oscillator. The reference clock drives a first predefined-bit shift register and the noisy clock drives a second predefined-bit shift register, where the second predefined-bit shift register is greater than the first predefined-bit shift register. When the first predefined-bit shift register overflows, the contents of the second predefined-bit shift register are evaluated. The contents of the second predefined-bit shift register are compared with a noise threshold select value to identify a noise event and trigger a noise detector control output.