The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
May. 24, 2011
Min-chul Shin, Yongin, KR;
Kyu-sik Cho, Yongin, KR;
Won-kyu Lee, Yongin, KR;
Tae-hoon Yang, Yongin, KR;
Byoung-kwon Choo, Yongin, KR;
Yun-gyu Lee, Yongin, KR;
Yong-hwan Park, Yongin, KR;
Sang-ho Moon, Yongin, KR;
Bo-kyung Choi, Yongin, KR;
Min-Chul Shin, Yongin, KR;
Kyu-Sik Cho, Yongin, KR;
Won-Kyu Lee, Yongin, KR;
Tae-Hoon Yang, Yongin, KR;
Byoung-Kwon Choo, Yongin, KR;
Yun-Gyu Lee, Yongin, KR;
Yong-Hwan Park, Yongin, KR;
Sang-Ho Moon, Yongin, KR;
Bo-Kyung Choi, Yongin, KR;
Samsung Display Co., Ltd., Yongin, KR;
Abstract
A display device with the substrate divided into three areas. A semiconductor layer is formed in the first second areas and includes a channel area and source/drain areas; a gate insulating layer formed on the semiconductor layer in an area corresponding to the channel area; and a gate electrode formed on the gate insulating layer. The source/drain electrodes contact the source/drain areas, respectively; a pixel electrode is formed in the same layer but in a third area; an interlayer insulating layer is formed on a whole surface of the substrate including the formed structures; and a gate line is formed on the interlayer insulating layer and is electrically connected to a gate electrode of the first area through a via contact hole of the interlayer insulating layer.