The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 20, 2013
Filed:
Dec. 02, 2011
Andrew T S Pomerene, Leesburg, VA (US);
Craig M. Hill, Warrenton, VA (US);
Timothy J. Conway, Gainesville, VA (US);
Stewart L. Ocheltree, Manassas, VA (US);
Andrew T S Pomerene, Leesburg, VA (US);
Craig M. Hill, Warrenton, VA (US);
Timothy J. Conway, Gainesville, VA (US);
Stewart L. Ocheltree, Manassas, VA (US);
BAE Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);
Abstract
A method for integrating a slotted waveguide into a CMOS process is disclosed. A slot can be patterned on a SOI wafer by etching a first pad hard mask deposited over the wafer. The slot is then filled with a nitride plug material by depositing a second pad hard mask over the first pad hard mask. A waveguide in association with one or more electronic and photonic devices can also be patterned on the SOI wafer. The trenches can be filled with an isolation material and then polished. Thereafter, the first and second pad hard masks can be stripped from the wafer. The slot can once again be filled with the nitride plug material and patterned. After forming one or more electronic and photonic devices on the wafer using a standard CMOS process, a via can be opened down to the nitride plug and the nitride plug can then be removed.