Semiconductor integrated device and operation method thereof

Abstract

In a semiconductor integrated circuit, having a central processing unit, a clock generating unit, an A/D converter and a sample and hold signal generating circuit, noise from an element that operates in accordance with operation timing that is difficult to predict beforehand is reduced. In a calibration operation, in response to a clock signal from the clock generating unit, a sample and hold signal generating circuit supplies a plurality of clock signals sequentially to a sample and hold circuit of the A/D converter. By analyzing a plurality of digital signals that are sequentially output from an A/D conversion circuit of the A/D converter, a timing of a holding period for allowing A/D conversion under a low noise condition is selected from the clock signals. In normal operation, a clock signal selected by the calibration operation is supplied as a sample and hold control signal to the sample and hold circuit.