The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2013

Filed:

Oct. 17, 2011
Applicant:

Vishnu Ravinuthula, Allen, TX (US);

Inventor:

Vishnu Ravinuthula, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/03 (2006.01); H03L 1/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region.


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