The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 13, 2013

Filed:

Feb. 11, 2009
Applicants:

Andrea Morello, Surry Hills, AU;

Andrew Dzurak, Darlinghurst, AU;

Hans-gregor Huebl, Munich, DE;

Robert Graham Clark, Balgowlah Heights, AU;

Laurens Henry Willems Van Beveren, Sydney, AU;

Lloyd Christopher Leonard Hollenberg, Camberwell, AU;

David Normal Jamieson, Eltham, AU;

Christopher Escott, Randwick, AU;

Inventors:

Andrea Morello, Surry Hills, AU;

Andrew Dzurak, Darlinghurst, AU;

Hans-Gregor Huebl, Munich, DE;

Robert Graham Clark, Balgowlah Heights, AU;

Laurens Henry Willems Van Beveren, Sydney, AU;

Lloyd Christopher Leonard Hollenberg, Camberwell, AU;

David Normal Jamieson, Eltham, AU;

Christopher Escott, Randwick, AU;

Assignee:

Qucor Pty Limited, Sydney, New South Wales, AU;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

This invention concerns an electronic device for the control and readout of the electron or hole spin of a single dopant in silicon. The device comprises a silicon substrate in which there are one or more ohmic contact regions. An insulating region on top of the substrate. First and second barrier gates spaced apart to isolate a small region of charges to form an island of a Single Electron Transistor (SET). A third gate over-lying both the first and second barrier gates, but insulated from them, the third gate being able to generate a gate-induced charge layer (GICL) in the beneath it. A fourth gate in close proximity to a single dopant atom, the dopant atom being encapsulated in the substrate outside the region of the GICL but close enough to allow spin-dependent charge tunnelling between the dopant atom and the SET island under the control of gate potentials, mainly the fourth gate. In use either the third or fourth gate also serve as an Electron Spin Resonance (ESR) line to control the spin of the single electron or hole of the dopant atom. In a further aspect it concerns a method for using the device.


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