The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2013
Filed:
Oct. 29, 2009
Richard K. Eguchi, Austin, TX (US);
Thomas S. Harp, Austin, TX (US);
Thomas Jew, Austin, TX (US);
Peter J. Kuhn, Austin, TX (US);
Timothy J. Strauss, Austin, TX (US);
Richard K. Eguchi, Austin, TX (US);
Thomas S. Harp, Austin, TX (US);
Thomas Jew, Austin, TX (US);
Peter J. Kuhn, Austin, TX (US);
Timothy J. Strauss, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.