The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2013

Filed:

Nov. 30, 2010
Applicants:

Daisuke Muraoka, Chiba, JP;

Minoru Ariyama, Chiba, JP;

Tomoki Hikichi, Chiba, JP;

Manabu Fujimura, Chiba, JP;

Inventors:

Daisuke Muraoka, Chiba, JP;

Minoru Ariyama, Chiba, JP;

Tomoki Hikichi, Chiba, JP;

Manabu Fujimura, Chiba, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 33/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a magnetic sensor device capable of suppressing a variation in determination for detection or canceling of a magnetic field intensity, which is caused by noise generated from respective constituent elements included in the magnetic sensor device and external noise, to thereby achieve high-precision magnetic reading. The magnetic sensor device includes: a first D-type flip-flop and a second D-type flip-flop each having an input terminal connected to an output terminal of a comparator; an XOR circuit having a first input terminal and a second input terminal which are connected to an output terminal of the first D-type flip-flop and an output terminal of the second D-type flip-flop, respectively; a selector circuit; and a third D-type flip-flop having an input terminal connected to an output terminal of the selector circuit. The selector circuit includes: a first input terminal (A) and a second input terminal (B) which are connected to the output terminal of the second D-type flip-flop and an output terminal of the third D-type flip-flop, respectively; and a select terminal connected to an output terminal of the XOR circuit. The selector circuit selectively outputs input signals from the first input terminal (A) and the second input terminal (B), according to an output of the XOR circuit.


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