The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 06, 2013
Filed:
Dec. 29, 2008
Zoran Randjelovic, Marin, CH;
Maksimilijan Stiglic, Maribor, SI;
Zoran Randjelovic, Marin, CH;
Maksimilijan Stiglic, Maribor, SI;
EM Microelectronic-Marin SA, Marin, CH;
Abstract
The electronic circuit is intended to form with an antenna a responder that operates without resetting to zero when the power supply of the electronic circuit is switched on (without POR). To increase efficiency and reduce the costs of testing a plurality of such integrated circuits in a wafer, means are provided that allow the logic circuit () to be reset to zero during such a test by electrical contact with the pads (P, P) of each circuit by using two extractors (and) of clock signals (CLand CL) connected to the inputs of a generator () of a zero reset signal (SR). The state of the generator is essentially given by the difference in pulses received from the two clock signal extractors. As soon as the state of the generator corresponds to a value equal to or greater than a predefined integer, the logic circuit is reset to zero, which never occurs with the responder receiving an interrogation signal of a reader.