The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2013

Filed:

Oct. 27, 2006
Applicants:

James Norris Dieffenderfer, Apex, NC (US);

Anand Krishnamurthy, Cary, NC (US);

Clint Wayne Mumford, Apex, NC (US);

Jason Lawrence Panavich, Pittsboro, NC (US);

Ketan Vitthal Patel, Cary, NC (US);

Ravi Rajagopalan, Cary, NC (US);

Thomas Philip Speier, Holly Springs, NC (US);

Inventors:

James Norris Dieffenderfer, Apex, NC (US);

Anand Krishnamurthy, Cary, NC (US);

Clint Wayne Mumford, Apex, NC (US);

Jason Lawrence Panavich, Pittsboro, NC (US);

Ketan Vitthal Patel, Cary, NC (US);

Ravi Rajagopalan, Cary, NC (US);

Thomas Philip Speier, Holly Springs, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

The content and order of a predetermined sequence of hard-coded and/or quasi-programmable test patterns may be altered during a Built-In Self-Test (BIST) routine. As such, knowledge gained post design completion may be reflected in the selection and arrangement of available tests to be executed during a BIST routine. In one embodiment, a sequence of hard-coded and/or quasi-programmable tests is executed during a BIST routine by receiving test ordering information for the sequence of tests and executing the sequence of tests in an order indicated by the test ordering information. A corresponding BIST circuit comprises a storage element and a state machine. The storage element is configured to store test ordering information for the sequence of tests. The state machine is configured to execute the sequence of tests in an order indicated by the test ordering information.


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