The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 30, 2013

Filed:

Aug. 20, 2012
Applicants:

Federico A. Altolaguirre, Kaohsiung, TW;

Ming-dou Ker, Kaohsiung, TW;

Chua-chin Wang, Kaohsiung, TW;

Inventors:

Federico A. Altolaguirre, Kaohsiung, TW;

Ming-Dou Ker, Kaohsiung, TW;

Chua-Chin Wang, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); H01C 7/12 (2006.01); H02H 1/00 (2006.01); H02H 1/04 (2006.01); H02H 3/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

An ESD protection circuit with leakage current reduction function includes a silicon controlled rectifier, a first CMOS inverter, a first transistor, a current mirror, a PMOS capacitor and a resistor. The first CMOS inverter electrically connects with the silicon controlled rectifier. The first transistor comprises a first end, a second end and a third end, wherein the first end electrically connects with the silicon controlled rectifier and the first CMOS inverter, and the current mirror electrically connects with the third end of the first transistor. The PMOS capacitor electrically connects with the current mirror, and the resistor electrically connects with the first CMOS inverter, the second end of the first transistor and the PMOS capacitor.


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