The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 30, 2013
Filed:
Aug. 20, 2009
Applicants:
Stephen John Hill, Cambridge, GB;
Michael Peter Muller, Cambridge, GB;
Inventors:
Stephen John Hill, Cambridge, GB;
Michael Peter Muller, Cambridge, GB;
Assignee:
ARM Limited, Cambridge, GB;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
Abstract
An integrated circuit () comprising an array () of interconnected configurable logic elements (), such as an FPGA array, is provided. The logic elements are used to form a power controller () which separately controls the power state of different regions of the array. Each region of the array contains one or more logic elements. Each region has a corresponding region controller () responsive to one or more power signals generated by the power controller to switch that region into the requested power state.