The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2013

Filed:

Jun. 28, 2012
Applicants:

Minsik Cho, Austin, TX (US);

Ruchir Puri, Baldwin PLace, NY (US);

Haoxing Ren, Austin, TX (US);

Hua Xiang, Ossining, NY (US);

Matthew M. Ziegler, Sleepy Hollow, NY (US);

Inventors:

Minsik Cho, Austin, TX (US);

Ruchir Puri, Baldwin PLace, NY (US);

Haoxing Ren, Austin, TX (US);

Hua Xiang, Ossining, NY (US);

Matthew M. Ziegler, Sleepy Hollow, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.


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