The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2013

Filed:

Dec. 04, 2009
Applicants:

Ilias Iliadis, Rueschlikon, CH;

Theodoros A. Antonakopoulos, Patras, GR;

Roman Pletka, Rueschlikon, CH;

Xiao-yu HU, Rueschlikon, CH;

Roy D. Cideciyan, Rueschlikon, CH;

Inventors:

Ilias Iliadis, Rueschlikon, CH;

Theodoros A. Antonakopoulos, Patras, GR;

Roman Pletka, Rueschlikon, CH;

Xiao-Yu Hu, Rueschlikon, CH;

Roy D. Cideciyan, Rueschlikon, CH;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for intra-block wear leveling within solid-state memory subjected to wear, having a plurality of memory cells includes the step of writing to at least certain ones of the plurality of memory cells, in a non-uniform manner, such as to balance the wear of the at least certain ones of the plurality of memory cells within the solid-state memory, at intra-block level. For example, if a behavior of at least some of the plurality of memory cells is not characterized, then the method may comprise characterizing a behavior of at least some of the plurality of memory cells and writing to at least certain ones of the plurality of memory cells, based on the characterized behavior, and in a non-uniform manner.


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