The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2013

Filed:

Apr. 07, 2011
Applicants:

Pascal Guenard, Froges, FR;

Bruce Faure, Paris, FR;

Fabrice Letertre, Meylan, FR;

Michael R. Krames, Los Altos, CA (US);

Nathan F. Gardner, Sunnyvale, CA (US);

Melvin B. Mclaurin, Mountain View, CA (US);

Inventors:

Pascal Guenard, Froges, FR;

Bruce Faure, Paris, FR;

Fabrice Letertre, Meylan, FR;

Michael R. Krames, Los Altos, CA (US);

Nathan F. Gardner, Sunnyvale, CA (US);

Melvin B. McLaurin, Mountain View, CA (US);

Assignee:

Soitec, Bernin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer.


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