The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2013

Filed:

Apr. 30, 2010
Applicants:

Kyoko Izuha, Kanagawa, JP;

Shunichi Shibuki, Kanagawa, JP;

Takashi Sakairi, Kumamoto, JP;

Inventors:

Kyoko Izuha, Kanagawa, JP;

Shunichi Shibuki, Kanagawa, JP;

Takashi Sakairi, Kumamoto, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a semiconductor device includes the steps of reading physical layout data of a circuit to be manufactured and performing calculation to modify a pattern width in the physical layout data by a predetermined amount; reading a physical layout and analyzing a pattern that is predicted to remain as a step difference of a predetermined amount or more in a case where a planarization process is performed on a planarizing film on a pattern by a quantitative calculation by using at least one of a density of patterns, a pattern width, and a peripheral length of a range of interest and a range in the vicinity of the range of interest; and reading data of the pattern that is predicted to remain as a step difference, and making a correction to a layout in which a step difference of a predetermined amount or more does not remain.


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