The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 16, 2013
Filed:
Apr. 13, 2009
Min Ming Tarng, San Jose, CA (US);
Mei Jech Lin, San Jose, CA (US);
Eric Yu-shiao Tarng, San Jose, CA (US);
Alfred Yu-chi Tarng, San Jose, CA (US);
Angela Yu-shiu Tarng, San Jose, CA (US);
Jwu-ing Tarng, San Jose, CA (US);
Huang-chang Tarng, San Jose, CA (US);
Shun-yu Nieh, San Jose, CA (US);
Min Ming Tarng, San Jose, CA (US);
Mei Jech Lin, San Jose, CA (US);
Eric Yu-Shiao Tarng, San Jose, CA (US);
Alfred Yu-Chi Tarng, San Jose, CA (US);
Angela Yu-Shiu Tarng, San Jose, CA (US);
Jwu-Ing Tarng, San Jose, CA (US);
Huang-Chang Tarng, San Jose, CA (US);
Shun-Yu Nieh, San Jose, CA (US);
Tang System, San Jose, CA (US);
Abstract
The Anlinx™:LVLP Hybrid Analogic Field Programmable Array of Milinx™:Mixed Signal FPSC™ Field Programmable System Chip™ is constituted of Field Programmable Hybrid Array (FPHA and Frequency Programmable Xtaless Clock (FPXC) being for high-speed and high frequency System-Design-On-Chip(SDOC) embedded in a single chip of Field Programmable System Chip(FPSC™). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application. The PLLess CDR and pipeline ADC are for the analog front high frequency application. With the SDOC on FPHA, the Automobile Infotainment Center(MIC) is reduced to be Mobile Infotainment Center(MIC). The (1) Capacitorless Low Drop Voltage (Capless LDVR) (2) Inductor less Switch Mode Power Supply (Indless SMPS) (3) Resistorless Current Sensor (Resless CS), (4) Saw Filter Less Low Noise Amplifier(Sawless LNA), (5) Diode Less True Random Number Generator (Dioless TRNG), (6) Crystal Less Clock (Xtaless Clock), (7) PLL Less Clock and Data Recovery (PLLess CDR) and (8) Filmless Touching Screen (FLTS) constitutes the most advanced System Design On Chip (SDOC) on Field Programmable Hybrid Array (FPHA) for Mobile Infotainment Center (MIC).