The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2013

Filed:

Apr. 25, 2011
Applicants:

Chung-che Yu, New Taipei, TW;

Kuo-wei Peng, New Taipei, TW;

Li-min Lee, New Taipei, TW;

Inventors:

Chung-Che Yu, New Taipei, TW;

Kuo-Wei Peng, New Taipei, TW;

Li-Min Lee, New Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A MOSFET layout is disclosed. The MOSFET comprises a drain region, a gate region, a source region and a body region. The gate region is disposed outside the drain region and adjacent to the drain region. The source region has a plurality of source sections, which are disposed outside of the gate region and adjacent to the gate region. Each of two adjacent source sections has a source blank zone there between. The body region has at least two body portions, which are disposed at the source blank zones and adjacent to the gate region.


Find Patent Forward Citations

Yu, Chung-Che. (2013). Mosfet layout and structure with common source (U.S. Patent No. 8487377). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8487377

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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