The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2013

Filed:

Oct. 19, 2009
Applicants:

John Divirgilio, Washingtonville, NY (US);

Liana L. Fong, Irvington, NY (US);

John Lewars, New Paltz, NY (US);

Seetharami R. Seelam, Yorktown Heights, NY (US);

Brian F. Veale, Cedar Park, TX (US);

Inventors:

John Divirgilio, Washingtonville, NY (US);

Liana L. Fong, Irvington, NY (US);

John Lewars, New Paltz, NY (US);

Seetharami R. Seelam, Yorktown Heights, NY (US);

Brian F. Veale, Cedar Park, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 13/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, information processing system, and computer program product are provided for managing operating system interference on applications in a parallel processing system. A mapping of hardware multi-threading threads to at least one processing core is determined, and first and second sets of logical processors of the at least one processing core are determined. The first set includes at least one of the logical processors of the at least one processing core, and the second set includes at least one of a remainder of the logical processors of the at least one processing core. A processor schedules application tasks only on the logical processors of the first set of logical processors of the at least one processing core. Operating system interference events are scheduled only on the logical processors of the second set of logical processors of the at least one processing core.


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