The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Mar. 23, 2010
Ravindraraj Ramaraju, Round Rock, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Gary A. Mussemann, Austin, TX (US);
Mihir S. Sabnis, Austin, TX (US);
Ravindraraj Ramaraju, Round Rock, TX (US);
Prashant U. Kenkare, Austin, TX (US);
Gary A. Mussemann, Austin, TX (US);
Mihir S. Sabnis, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A digital scan chain system having test scan has a plurality of flip-flop modules, each of the plurality of flip-flop modules having a first data bit input, a second data bit input, a test bit input, a clock input, a first data bit output, a second data bit output, and a test bit output. The test bit output of a first flip-flop module is directly connected to the test bit input of a second flip-flop module with no intervening circuitry. First and second multiplexed master/slave flip-flops are directly serially connected. A clocked latch is coupled to the output of the second multiplexed master/slave flip-flop and provides the test bit output. The clocked latch is clocked only during a test mode to save power.