The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Aug. 11, 2010
Daniel C. Espinosa, North Bethesda, MD (US);
Alessandro Geist, Bethesda, MD (US);
David J. Petrick, Severna Park, MD (US);
Thomas P. Flatley, Huntington, MD (US);
Jeffrey C. Hosler, Annapolis, MD (US);
Gary A. Crum, Silver Spring, MD (US);
Manuel Buenfil, Olney, MD (US);
Daniel C. Espinosa, North Bethesda, MD (US);
Alessandro Geist, Bethesda, MD (US);
David J. Petrick, Severna Park, MD (US);
Thomas P. Flatley, Huntington, MD (US);
Jeffrey C. Hosler, Annapolis, MD (US);
Gary A. Crum, Silver Spring, MD (US);
Manuel Buenfil, Olney, MD (US);
Abstract
A processing system including an FPGA having a dual port RAM and for use in hostile environments. The FPGA includes three portions: a C&DH portion; a first scratch pad portion receiving a first set of data, processing the first set of data, and outputting a first set of processed data to a first location of the RAM; and a second scratch pad portion receiving a second set of data identical to the first set of data, processing the second set of data in the same way that the first set of data is processed, and outputting a second set of processed data to a second location of the RAM. The C&DH portion compares the first set of processed data to the second set of processed data and, if the first set of processed data is the same as the second set of processed data, outputs one set of processed data.