The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2013

Filed:

Mar. 18, 2009
Applicants:

David G. Carlson, Rochester, MN (US);

Travis M. Drucker, Rochester, MN (US);

Timothy J. Mullins, Blaine, MN (US);

Jeffrey S. Mcallister, St. Paul, MN (US);

Nelson Ramirez, Rochester, MN (US);

Inventors:

David G. Carlson, Rochester, MN (US);

Travis M. Drucker, Rochester, MN (US);

Timothy J. Mullins, Blaine, MN (US);

Jeffrey S. McAllister, St. Paul, MN (US);

Nelson Ramirez, Rochester, MN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01); G06F 9/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures.


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