The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 09, 2013
Filed:
Apr. 27, 2010
Jürgen Lerzer, Neumarkt/OPf, DE;
Stefan Meyer, Hoechstadt, DE;
Stefan Strobl, Obermichelbach, DE;
Telefonaktiebolaget LM Ericsson (Publ), Stockholm, SE;
Abstract
A distributed memory architecture for a layer 2 processing circuit chip () is described. In one implementation, the layer 2 processing circuit chip () comprises an external memory interface configured to provide access to data packets stored in an external memory (), a layer 2 processor () coupled to the external memory interface () and configured to process data packets retrieved from the external memory () to generate RLC SDUs, and an on-chip memory () coupled to the layer 2 processor () and configured to store the RLC PDUs generated by the layer 2 processor () prior to their transmission. Upon a request to retransmit an RLC PDU, the layer 2 processor () is configured to selectively read the RLC PDU to be retransmitted from the on-chip memory () or a data packet comprising the RLC PDU to be retransmitted from the external memory (). In the latter case, the layer 2 processor () is further configured to re-generate the RLC PDU to be retransmitted from the data packet read from the external memory (). The selectivity of the read operation depends on whether or not the RLC PDU to be retransmitted belongs to a data packet that has been completely transmitted in a single layer 1 transport unit.