The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2013

Filed:

Sep. 16, 2011
Applicants:

Hao-yuan Howard Chou, San Jose, CA (US);

Wei Zhang, San Jose, CA (US);

Haiming Yu, Pleasanton, CA (US);

Inventors:

Hao-Yuan Howard Chou, San Jose, CA (US);

Wei Zhang, San Jose, CA (US);

Haiming Yu, Pleasanton, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01); G11C 11/00 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.


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