The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2013

Filed:

Jun. 03, 2011
Applicant:

Hideki Hirayama, Gifu-ken, JP;

Inventor:

Hideki Hirayama, Gifu-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05B 19/408 (2006.01);
U.S. Cl.
CPC ...
Abstract

In an adder circuit, a sine wave is added to a compensation signal which is generated based on a position detection signal of a member to be driven and for compensating a position of a lens which is the member to be driven. An absolute value integrating circuit integrates absolute values of signals before and after the adder circuit adds the sine wave. The two obtained integrated values are compared by a comparator circuit, and a gain adjusting circuit adjusts a gain of an amplifier which amplifies the compensation signal so that the two integrated values are equal to each other.


Find Patent Forward Citations

Hirayama, Hideki. (2013). Loop gain adjusting circuit (U.S. Patent No. 8482239). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8482239

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…