The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Mar. 02, 2011
Lewis W. Dewey, Iii, Wappingers Falls, NY (US);
Ning LU, Essex Junction, VT (US);
Judith H. Mccullen, Essex Junction, VT (US);
Cole E. Zemke, Essex Junction, VT (US);
Lewis W. Dewey, III, Wappingers Falls, NY (US);
Ning Lu, Essex Junction, VT (US);
Judith H. McCullen, Essex Junction, VT (US);
Cole E. Zemke, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method calculates a total source/drain resistance for a field effect transistor (FET) device. The method counts the number (N) of contacts in each source/drain region of the FET device, partitions each source/drain region into N contact regions and calculates a set of resistances of elements and connections to the FET device. The measured dimensions of widths, lengths, and distances of layout shapes forming the FET and the connections to the FET are determined and a set of weights based on relative widths of the contact regions are computed. The total source/drain resistance of the FET device is determined by summing products of the set of resistances and the set of weights for each of a plurality of contacts in series, the summing being performed for all of the plurality of contacts in one of a source region and a drain region of the FET. A netlist is formed based on the total source resistance and total drain resistance of the FET device.