The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Jun. 01, 2010
Applicants:

Han Henry Sun, Ottawa, CA;

Kuang-tsan Wu, Kanata, CA;

Yuejian Wu, Ottawa, CA;

Sandy Thomson, Ottawa, CA;

John D. Mcnicol, Ottawa, CA;

David J. Krause, Nepean, CA;

Inventors:

Han Henry Sun, Ottawa, CA;

Kuang-Tsan Wu, Kanata, CA;

Yuejian Wu, Ottawa, CA;

Sandy Thomson, Ottawa, CA;

John D. McNicol, Ottawa, CA;

David J. Krause, Nepean, CA;

Assignee:

Infinera Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system, method, and apparatus is disclosed for interpolation of an output of an analog to digital converter (ADC) to enable operation of the ADC at a sampling rate that is independent of the sampling rate for a DSP core so as to efficiently enable operation at higher date rates. According to one of the embodiments, an interpolation circuit is coupled between the ADC and DSP core and receives a first plurality of samples of data at the first data rate from the ADC and supplies a plurality of samples of second data at a second data rate to the DSP core; the second data rate being less than the first data rate. According to one of the embodiments, the interpolation circuit includes a memory and a FIR filter circuit having filter tap coefficient values selected to provide attenuation at high frequencies to reduce aliasing noise.


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