The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Aug. 25, 2011
Applicants:

Joel A. Silberman, Somers, NY (US);

Matthew R. Wordeman, Kula, HI (US);

Inventors:

Joel A. Silberman, Somers, NY (US);

Matthew R. Wordeman, Kula, HI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/04 (2006.01); H03K 3/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a synchronization circuit for a 3D chip stack having multiple circuits and multiple strata interconnected using a first and a second stack-wide broadcast connection chain. The synchronization circuit includes the following, on each stratum. A synchronizer connected to the first connection chain receives an asynchronous signal therefrom and performs a synchronization to provide a synchronous signal. A driver is connected to the second chain for driving the synchronous signal. A latch connected to the second chain receives the synchronous signal driven by the driver on a same or different stratum within a next clock cycle from the synchronization to provide the stack-wide synchronous signal to a circuit on a same stratum. An output of a single driver on one stratum is selected at any given time for use by the latch on all strata.


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