Latch circuit with single node single-event-upset immunity

Abstract

A latch circuit, such as a memory cell or a flip-flop, that is immune to single-event upset at any single node. The latch circuit includes two banks of four logic gates each. The output of each logic gate in the first bank is connected to inputs of two logic gates in the second bank, and the output of each logic gate in the second bank is connected to inputs of two logic gates in the first bank. Each logic gate includes a logic function receiving an input node and an enable signal, such as a load signal. The interconnection of the logic gates corrects single-event upset at any one of the nodes. In the memory cell arrangement, redundant data paths are used to produce two input nodes provides single-event upset immunity at those input nodes. A layout of the latch circuit that ensures that random ionization affects only a single node is also disclosed.