The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2013
Filed:
Nov. 14, 2011
John Henry Bui, Sunnyvale, CA (US);
Lay Hock Khoo, Georgetown, MY;
Khai Nguyen, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Ket Chiew Sia, Bayan Lepas, MY;
John Henry Bui, Sunnyvale, CA (US);
Lay Hock Khoo, Georgetown, MY;
Khai Nguyen, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Ket Chiew Sia, Bayan Lepas, MY;
Altera Corporation, San Jose, CA (US);
Abstract
Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.