The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

Feb. 23, 2010
Applicants:

Izumi Hirano, Fujisawa, JP;

Yuichiro Mitani, Kanagawa-Ken, JP;

Tatsuo Shimizu, Tokyo, JP;

Yasushi Nakasaki, Yokohama, JP;

Akiko Masada, Tokyo, JP;

Shigeto Fukatsu, Yokohama, JP;

Masahiro Koike, Yokohama, JP;

Inventors:

Izumi Hirano, Fujisawa, JP;

Yuichiro Mitani, Kanagawa-Ken, JP;

Tatsuo Shimizu, Tokyo, JP;

Yasushi Nakasaki, Yokohama, JP;

Akiko Masada, Tokyo, JP;

Shigeto Fukatsu, Yokohama, JP;

Masahiro Koike, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×10cmto 2.96×10cm, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.


Find Patent Forward Citations

Hirano, Izumi. (2013). Semiconductor device including a gate insulating film having a metal oxide layer having trap levels (U.S. Patent No. 8476718). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8476718

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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