The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2013

Filed:

May. 17, 2011
Applicants:

Dong-ju Yang, Seoul, KR;

Yu-gwang Jeong, Yongin-si, KR;

Jean-ho Song, Yongin-si, KR;

Ki-yeup Lee, Yongin-si, KR;

Shin-il Choi, Hwaseong-si, KR;

Tae-woo Kim, Seongnam-si, KR;

Inventors:

Dong-Ju Yang, Seoul, KR;

Yu-Gwang Jeong, Yongin-si, KR;

Jean-Ho Song, Yongin-si, KR;

Ki-Yeup Lee, Yongin-si, KR;

Shin-Il Choi, Hwaseong-si, KR;

Tae-Woo Kim, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a thin film transistor array panel includes forming a gate line; forming an insulating layer on the gate line; forming first and second silicon layers first and second metal layers; forming a photoresist pattern having first and second portions; forming first and second metal patterns by etching the first and second metal layers; processing the first metal pattern with SFor SF/He; forming silicon and semiconductor patterns by etching the second and first silicon layers; removing the first portion of the photoresist pattern; forming an upper layer of a data wire by wet etching the second metal pattern; forming a lower layer of the data wire and an ohmic contact by etching the first metal and amorphous silicon patterns; forming a passivation layer including a contact hole on the upper layer; and forming a pixel electrode on the passivation layer.


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