The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2013

Filed:

Oct. 01, 2007
Applicants:

Shinji Hara, Tokyo, JP;

Daisuke Miyauchi, Tokyo, JP;

Koji Shimazawa, Tokyo, JP;

Yoshihiro Tsuchiya, Tokyo, JP;

Tomohito Mizuno, Tokyo, JP;

Takahiko Machita, Tokyo, JP;

Inventors:

Shinji Hara, Tokyo, JP;

Daisuke Miyauchi, Tokyo, JP;

Koji Shimazawa, Tokyo, JP;

Yoshihiro Tsuchiya, Tokyo, JP;

Tomohito Mizuno, Tokyo, JP;

Takahiko Machita, Tokyo, JP;

Assignee:

TDK Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11B 5/33 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention provides a giant magneto-resistive effect device of the CPP (current perpendicular to plane) structure (CPP-GMR device) comprising a spacer layer, and a first ferromagnetic layer and a second ferromagnetic layer stacked together with said spacer layer sandwiched between them, with a sense current passed in the stacking direction, wherein the first ferromagnetic layer and the second ferromagnetic layer function such that the angle made between the directions of magnetizations of both layers change relatively depending on an external magnetic field, said spacer layer contains a semiconductor oxide layer, and a nitrogen element-interface protective layer is provided at a position where the semiconductor oxide layer forming the whole or a part of said spacer layer contacts an insulating layer. Thus, there is a nitride of high covalent bonding capability formed at the surface of junction between the semiconductor oxide layer and the interface protective layer, so that the migration of oxygen from the semiconductor oxide layer to the insulating layer is inhibited; even when the device undergoes heat and stress in the process, fluctuations and deteriorations of device characteristics are held back.


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