The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 18, 2013
Filed:
Apr. 22, 2009
Applicants:
Zahir Parpia, Toronto, CA;
Chris Wysocki, Toronto, CA;
Vaughn Betz, Toronto, CA;
Inventors:
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.