The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2013

Filed:

Jan. 28, 2011
Applicants:

Barry M. Lunt, Provo, UT (US);

Matthew R. Linford, Provo, UT (US);

Robert C. Davis, Provo, UT (US);

Dee Anderson, Provo, UT (US);

Inventors:

Barry M. Lunt, Provo, UT (US);

Matthew R. Linford, Provo, UT (US);

Robert C. Davis, Provo, UT (US);

Dee Anderson, Provo, UT (US);

Assignee:

Brigham Young University, Provo, UT (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/00 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A permanent solid state memory device is disclosed. Recording data in the permanent solid state memory device forms voids in a data layer between a first wire array and a second wire array. Wires of the first wire array extend transversely to wires in the second wire array. The data layer is at least partially conductive such that a voltage applied between a selected first wire in the first wire array and a selected second wire in the second wire array creates a heating current through the data layer at a data point between the first wire and the second wire. The heating current causes a data layer material to melt and recede to form a permanent void. Control elements are operably connected to apply voltages to predetermined combinations of wires to form permanent voids at data points throughout the solid state memory device.


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