The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Jun. 04, 2008
Applicants:

Ramaswamy Sivaramakrishnan, San Jose, CA (US);

Connie Cheung, Sunnyvale, CA (US);

William Bryg, Saratoga, CA (US);

Inventors:

Ramaswamy Sivaramakrishnan, San Jose, CA (US);

Connie Cheung, Sunnyvale, CA (US);

William Bryg, Saratoga, CA (US);

Assignee:

Oracle America, Inc., Redwood City, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/06 (2006.01); G06F 15/16 (2006.01);
U.S. Cl.
CPC ...
Abstract

A distributed shared memory multiprocessor system that supports both fine- and coarse- grained interleaving of the shared memory address space. A ceiling mask sets a boundary between the fine-grain interleaved and coarse-grain interleaved memory regions of the distributed shared memory. A method for satisfying a memory access request in a distributed shared memory subsystem of a multiprocessor system having both fine- and coarse-grain interleaved memory segments. Certain low or high order address bits, depending on whether the memory segment is fine- or coarse-grain interleaved, respectively, are used to determine if the memory address is local to a processor node. A method for setting the ceiling mask of a distributed shared memory multiprocessor system to optimize performance of a first application run on a single node and performance of a second application run on a plurality of nodes.


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