The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Oct. 06, 2010
Applicants:

Ian Michael Charles Shand, Cobham, GB;

Stewart Frederick Bryant, Merstham, GB;

Inventors:
Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, two neighboring nodes adjacent to each end-point node of a domain may be associated with a 'dual' (a logical structure). A first of the two neighboring nodes may be placed into a first family (and group) of the dual, while a second of the two neighboring nodes may be placed into an opposing second family (and group). Augmentations may then be performed, recursively merging and connecting the duals and/or groups, as well as connecting unplaced nodes to particular duals, families, and groups, according to forced augmentations and/or unforced augmentations where no forced augmentations exist. In the end, it may be determined whether the domain supports dual plane topologies based on whether a solution having one resultant dual with a single group in each opposing family is reached from the recursive augmentations.


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