The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Apr. 08, 2011
Applicants:

Sameer M. Venugopal, San Jose, CA (US);

David R. Allee, Phoenix, AZ (US);

Lawrence T. Clark, Phoenix, AZ (US);

Inventors:

Sameer M. Venugopal, San Jose, CA (US);

David R. Allee, Phoenix, AZ (US);

Lawrence T. Clark, Phoenix, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Embodiments and examples of differential threshold voltage non-volatile memories and related methods are described herein. In one example, a method for providing an integrated circuit can comprise providing a memory cell coupled to a first bitline and to a second bitline, and at least one of (a) providing a read assist mechanism configured to couple to the memory cell via the first and second bitlines, or (b) providing a memory reset mechanism configured to couple to the memory cell via the first and second bitlines. Providing the memory cell can comprise providing a first transistor comprising a first threshold voltage, providing a second transistor comprising a second threshold voltage, and cross-coupling the first and second transistors of the memory cell together. A difference between the first and second threshold voltages can correspond to a logic state of the memory cell. Other embodiments, examples, and related methods are also disclosed herein.


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