The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2013
Filed:
Nov. 18, 2011
Ankur Goel, Haryana, IN;
Donald Albert Evans, Carroll, OH (US);
Dennis Edward Dudeck, Hazle Township, PA (US);
Richard John Stephani, Saint Paul, MN (US);
Ronald James Wozniak, Whitehall, PA (US);
Dharmendra Kumar Rai, Uttar Predish, IN;
Rasoju Veerabadra Chary, Karnataka, IN;
Jeffrey Charles Herbert, Narareth, PA (US);
Ankur Goel, Haryana, IN;
Donald Albert Evans, Carroll, OH (US);
Dennis Edward Dudeck, Hazle Township, PA (US);
Richard John Stephani, Saint Paul, MN (US);
Ronald James Wozniak, Whitehall, PA (US);
Dharmendra Kumar Rai, Uttar Predish, IN;
Rasoju Veerabadra Chary, Karnataka, IN;
Jeffrey Charles Herbert, Narareth, PA (US);
LSI Corporation, San Jose, CA (US);
Abstract
A memory device comprises a memory block, a power gating transistor, and control circuitry. The memory block includes at least one memory cell comprising a storage element electrically connected to a source potential line, a drive strength of the storage element being a function of a voltage level on the source potential line. The power gating transistor, in turn, is connected between the source potential line and a voltage source. The control circuitry is operative to configure the power gating transistor to electrically connect the source potential line to the voltage source while the memory block is in a first mode, and to clamp the source potential line at a voltage different from that of the voltage source when the memory block is in a second mode.