The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 11, 2013

Filed:

Oct. 29, 2009
Applicants:

Akihiro Kawahara, Yokohama, JP;

Makoto Adachi, Yokohama, JP;

Kouji Nishikawa, Yokohama, JP;

Masayuki Nakamura, Yokohama, JP;

Motonobu Mamiya, Yokohama, JP;

Kae Yamashita, Yokohama, JP;

Inventors:

Akihiro Kawahara, Yokohama, JP;

Makoto Adachi, Yokohama, JP;

Kouji Nishikawa, Yokohama, JP;

Masayuki Nakamura, Yokohama, JP;

Motonobu Mamiya, Yokohama, JP;

Kae Yamashita, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory access control circuit includes a first internal register, an address transmitting unit that sets a state of the first internal register to a first state to transmit a first address and sets a state of the first internal register to a second state to transmit a second address, a second internal register, a data receiving unit that sets a state of the second internal register to a third state to receive first data corresponding to the first address, performs data processing on the first data without delay, sets a state of the second internal register to a fourth state to receive second data corresponding to the second address, and performs data processing on the second data after delaying the second data by a given delay time, a first backup unit and a second backup unit.


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